Field of the Invention
The present invention relates to a data processing technique, and in particular to a technique to apply a checksum operation to transfer data concurrently with DMA transfer.
Description of the Related Art
There are communication devices that transfer data to a communication partner by connecting to a network using TCP (Transmission Control Protocol)/IP (Internet Protocol) communication protocols. In recent years, there are an increasing number of situations where such communication devices transfer high-resolution, high-definition image data to each other. In order to enable broadband data transfer, it is vital that the communication devices execute communication protocol processing at high speed.
According to the TCP/IP communication protocols, a packet is formed by appending a header, such as an address of a transmission destination and an error correction code, to data to be transferred, and communication is performed in units of packets. A checksum is used for the error correction code, and is calculated by obtaining the one's complement of the one's complement sum of an entire packet.
As such, the TCP/IP communication protocols require application of calculation processing to an entire packet to obtain a checksum. Therefore, high-speed execution of this calculation processing is necessary to increase the speed of communication protocol processing.
In order to execute the above-described checksum operation at high speed, various apparatuses and control methods have been proposed so far, one of them being an operation circuit described in Japanese Patent Laid-Open No. 2008-129632. This operation circuit performs an operation of an arbitrary number of input data pieces by using DMA transfer according to a description of a descriptor, and outputs the operation result; in order to perform operation processing, it divides the arbitrary number of input data pieces into a plurality of pieces, instead of performing an operation of the arbitrary number of input data pieces at a time. The operation circuit stores an intermediate result for each of the divided operations in an external storage device, performs operation processing by reading the intermediate result in the next operation processing, and obtains a final result by repeating the same.
The operation circuit described in Japanese Patent Laid-Open No. 2008-129632 performs DMA transfer to execute operation processing, and applies operation processing to the entire data targeted for DMA transfer. However, the problem with the above-described conventional example is that it does not support operation processing applied to a portion of data targeted for DMA transfer (for example, the portion other than the header and the footer).